SH7050 Datasheet, PDF (62/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 2 CPU
Table 2.13 Arithmetic Operation Instructions
Instruction
ADD
Rm,Rn
ADD
#imm,Rn
ADDC Rm,Rn
ADDV Rm,Rn
CMP/EQ #imm,R0
CMP/EQ Rm,Rn
CMP/HS Rm,Rn
CMP/GE Rm,Rn
CMP/HI Rm,Rn
CMP/GT Rm,Rn
CMP/PL Rn
CMP/PZ Rn
CMP/STR Rm,Rn
DIV1 Rm,Rn
DIV0S Rm,Rn
DIV0U
Instruction Code
0011nnnnmmmm1100
0111nnnniiiiiiii
0011nnnnmmmm1110
0011nnnnmmmm1111
10001000iiiiiiii
Operation
Rn + Rm → Rn
Rn + imm → Rn
Rn + Rm + T → Rn,
Carry → T
Rn + Rm → Rn,
Overflow → T
If R0 = imm, 1 → T
Execu-
tion
Cycles
1
1
1
1
1
0011nnnnmmmm0000 If Rn = Rm, 1 → T
1
0011nnnnmmmm0010 If Rn≥Rm with
1
unsigned data, 1 → T
0011nnnnmmmm0011 If Rn ≥ Rm with signed 1
data, 1 → T
0011nnnnmmmm0110 If Rn > Rm with
1
unsigned data, 1 → T
0011nnnnmmmm0111 If Rn > Rm with signed 1
data, 1 → T
0100nnnn00010101 If Rn > 0, 1 → T
1
0100nnnn00010001 If Rn ≥ 0, 1 → T
1
0010nnnnmmmm1100 If Rn and Rm have
1
an equivalent byte,
1→T
0011nnnnmmmm0100 Single-step division
1
(Rn/Rm)
0010nnnnmmmm0111 MSB of Rn → Q, MSB 1
of Rm → M, M ^ Q → T
0000000000011001 0 → M/Q/T
1
T Bit
—
—
Carry
Overflow
Comparison
result
Comparison
result
Comparison
result
Comparison
result
Comparison
result
Comparison
result
Comparison
result
Comparison
result
Comparison
result
Calculation
result
Calculation
result
0
Rev. 5.00 Jan 06, 2006 page 42 of 818
REJ09B0273-0500