SH7050 Datasheet, PDF (820/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Appendix A On-Chip Supporting Module Registers
RAM Emulation Register (RAMER) H'FFFF8628
8/16/32
Bit: 15
14
13
12
11
10
Bit name: —
—
—
—
—
—
Initial value: 0
0
0
0
0
0
R/W: R
R
R
R
R
R
Flash Memory
9
8
—
—
0
0
R
R
Bit: 7
6
5
4
3
2
1
0
Bit name: —
—
—
—
— RAMS RAM1 RAM0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R/W R/W R/W
Bit
Bit Name
Value Description
2
RAM select (RAMS)
0
Emulation not selected
Write/erase protection disabled for all flash
memory blocks
(Initial value)
1
Emulation selected
Write/erase protection enabled for all flash memory
blocks
1, 0
RAM Area Specification
(RAM1, RAM0)
Selection of flash memory area overlapping RAM
RAM Area
H'FFFFE800–H'FFF EBFF
H'0001F000–H'0001F3FF
H'0001F400–H'0001F7FF
H'0001F800–H'0001FBFF
H'0001FC00–H'0001FFFF
RAMS
0
1
1
1
1
RAM1
*
0
0
1
1
RAM0
*
0
1
0
1
Rev. 5.00 Jan 06, 2006 page 800 of 818
REJ09B0273-0500