SH7050 Datasheet, PDF (279/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
TIERDL controls enabling/disabling of channel 4 and 5 input capture, compare-match, and
overflow interrupt requests.
Bit:
Initial value:
R/W:
7
OVE4
0
R/W
6
IME4D
0
R/W
5
IME4C
0
R/W
4
IME4B
0
R/W
3
IME4A
0
R/W
2
OVE5
0
R/W
1
IME5B
0
R/W
0
IME5A
0
R/W
Bit 7—Overflow Interrupt Enable (OVE4): Enables or disables interrupt requests by OVF4 in
TSR when OVF4 is set to 1.
Bit 7:
OVE4
0
1
Description
OVI4 interrupt requested by OVF4 is disabled
OVI4 interrupt requested by OVF4 is enabled
(Initial value)
Bit 6—Input Capture/Compare-Match Interrupt Enable (IME4D): Enables or disables
interrupt requests by IMF4D in TSR when IMF4D is set to 1.
Bit 6:
IME4D
0
1
Description
IMI4D interrupt requested by IMF4D is disabled
IMI4D interrupt requested by IMF4D is enabled
(Initial value)
Bit 5—Input Capture/Compare-Match Interrupt Enable (IME4C): Enables or disables
interrupt requests by IMF4C in TSR when IMF4C is set to 1.
Bit 5:
IME4C
0
1
Description
IMI4C interrupt requested by IMF4C is disabled
IMI4C interrupt requested by IMF4C is enabled
(Initial value)
Rev. 5.00 Jan 06, 2006 page 259 of 818
REJ09B0273-0500