SH7050 Datasheet, PDF (306/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
The ATU channel 6 to 9 counters (TCNT) all perform cyclic count operations unconditionally.
ATU channel 3 to 5 free-running counters (TCNT) perform synchronous count operation when 1
is set in bits T3PWM to T5PWM in the timer mode register (TMDR). These free-running counters
also perform synchronous count operation if the corresponding CCI bit in the timer I/O control
register (TIOR) is set to 1 when bits T3PWM to T5PWM are 0. The relevant TCNT counter is
cleared by a compare-match of TCNT with GR3D or GR4D in channel 3 or 4, GR5B in channel 5,
or CYLR in channels 6 to 9 (counter clear function). In this way, cyclic counting is performed.
TCNT starts counting up as a cyclic counter when the corresponding STR bit in TSTR is set to 1
after the TMDR setting is made. When the count value matches the GR3D, GR4D, GR5B, or
CYLR value, the corresponding IMF3D, IMF4D, or IMF5B bit in timer status register D (TSRD)
(or the CMF bit in TSRE for channels 6 to 9) is set to 1, and TCNT is cleared to H'0000 (H'0001
for channels 6 to 9). If the corresponding TIER bit is set to 1 at this time, an interrupt request is
sent to the CPU. After the compare-match, TCNT starts counting up again from H'0000 (H'0001
for channels 6 to 9).
Cyclic counter operation is shown in figure 10.12.
GR3D, GR4D,
GR5B, CYLR
Counter cleared on compare-match
H'0000
(channels 6 to 9: H'0001)
STR bit
in TSTR
IMF3D, IMF4D,
IMF5B, CMF
Time
Figure 10.12 Cyclic Counter Operation
10.3.3 Output Compare-Match Function
In ATU channels 1 to 5, waveform output is performed by means of output compare-matches at
the corresponding external pin (TIOA1 to TIOF1, TIOA2, TIOB2, TIOA3 to TIOD3, TIO4A to
TIOD4, TIOA5, TIOB5) by making an output compare-match specification for the timer I/O
control registers (TIOR0 to TIOR5). A free-running counter (TCNT) starts counting up when 1 is
set in the timer status register (TSTR). When the desired number is set beforehand in a general
register (GR1A to GR1F, GR2A, GR2B, GR3A to GR3D, GR4A to GR4D, GR5A, GR5B), and
the counter value matches the corresponding general register, a waveform is output from the
corresponding external pin.
Rev. 5.00 Jan 06, 2006 page 286 of 818
REJ09B0273-0500