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| SH7050 Datasheet, PDF (27/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/ | |||
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1.2 Block Diagram
Section 1 Overview
RES
HSTBY
MD3
MD2
MD1
MD0
NMI
WDTOVF
CK
EXTAL
XTAL
PLLVCC
PLLVSS
PLLCAP
VCC (Ã15)
VSS (Ã15)
AVref
AVCC (Ã2)
AVSS (Ã2)
FWE (NC*)
PH15/AN15
PH14/AN14
PH13/AN13
PH12/AN12
PH11/AN11
PH10/AN10
PH9/AN9
PH8/AN8
PH7/AN7
PH6/AN6
PH5/AN5
PH4/AN4
PH3/AN3
PH2/AN2
PH1/AN1
PH0/AN0
PB0/TO6
PB1/TO7
PB2/TO8
PB3/TO9
Port/control signals
Port/address signals
ROM (flash/mask)
RAM
Clock pulse
generator
CPU
Multiplier
Interrupt
controller
Direct memory
access
controller
(4 channels)
Bus state controller
Serial communi-
cation interface
(3 channels)
Compare-match
timer
(2 channels)
Advanced timer
unit
A/D Watchdog
converter timer
Port
Port
PD15/D15
PD14/D14
PD13/D13
PD12/D12
PD11/D11
PD10/D10
PD9/D9
PD8/D8
PD7/D7
PD6/D6
PD5/D5
PD4/D4
PD3/D3
PD2/D2
PD1/D1
PD0/D0
PG0/ADTRG/IRQOUT
PG1/SCK0
PG2/TxD0
PG3/RxD0
PG4/SCK1
PG5/TxD1
PG6/RxD1
PF8/SCK2/PULS4
PG7/TxD2
PG8/RxD2
PF0/IRQ0
PF1/IRQ1
PF2/IRQ2
PF3/IRQ3
PG14/IRQ4/TIOA5
PG15/IRQ5/TIOB5
PF7/DREQ0/PULS3
PF6/DACK0/PULS2
PF5/DREQ1/PULS1
PF4/DACK1/PULS0
Note: * MASK ROM version
Figure 1.1 Block Diagram
: Peripheral address bus (24 bits)
: Peripheral data bus (16 bits)
: Internal address bus (24 bits)
: Internal upper data bus (16 bits)
: Internal lower data bus (16 bits)
Rev. 5.00 Jan 06, 2006 page 7 of 818
REJ09B0273-0500
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