SH7050 Datasheet, PDF (120/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 7 User Break Controller (UBC)
7.2.3 User Break Bus Cycle Register (UBBR)
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
CP1 CP0
ID1
ID0
RW1 RW0
SZ1
SZ0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
User break bus cycle register (UBBR) is a 16-bit readable/writable register that selects from
among the following four break conditions:
1. CPU cycle/DMA cycle
2. Instruction fetch/data access
3. Read/write
4. Operand size (byte, word, longword)
UBBR is initialized by a power on reset to H'0000. It is not initialized in software standby mode.
Bits 15 to 8—Reserved: These bits always read as 0. The write value should always be 0.
Bits 7 and 6—CPU Cycle/Peripheral Cycle Select (CP1, CP0): These bits designate break
conditions for CPU cycles or peripheral cycles (DMA cycles).
Bit 7: CP1
0
1
Bit 6: CP0
0
1
0
1
Description
No user break interrupt occurs (initial value)
Break on CPU cycles
Break on peripheral cycles
Break on both CPU and peripheral cycles
Rev. 5.00 Jan 06, 2006 page 100 of 818
REJ09B0273-0500