SH7050 Datasheet, PDF (572/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 18 ROM (128 kB Version)
Start
Set pins to boot mode
and execute reset-start
Host transfers data (H'00)
continuously at prescribed bit rate
SH7050 measures low period
of H'00 data transmitted by host
SH7050 calculates bit rate and
sets value in bit rate register
After bit rate adjustment, SH7050
transmits one H'00 data byte to
host to indicate end of adjustment
Host confirms normal reception
of bit rate adjustment end
indication (H'00), and transmits
one H'55 data byte
After receiving H'55,
SH7050 transmits one H'AA
data byte to host
Host transmits number
of programming control program
bytes (N), upper byte followed
by lower byte
SH7050 transmits received
number of bytes to host as verify
data (echo-back)
n=1
Host transmits programming control
program sequentially in byte units
SH7050 transmits received
programming control program to
host as verify data (echo-back)
Transfer received programming
control program to on-chip RAM
n = N?
No
Yes
End of transmission
Check flash memory data, and
if data has already been written,
erase all blocks
After confirming that all flash
memory data has been erased,
SH7050 transmits one H'AA data
byte to host
Execute programming control
program transferred to on-chip RAM
n+1→n
Note: If a memory cell does not operate normally and cannot be erased, one H'FF byte is
transmitted as an erase error, and the erase operation and subsequent operations
are halted.
Figure 18.4 Boot Mode Execution Procedure
Rev. 5.00 Jan 06, 2006 page 552 of 818
REJ09B0273-0500