SH7050 Datasheet, PDF (329/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
OSF Setting Timing in Underflow: When a down-counter (DCNT) counts down from H'0001 to
H'0000 on DCNT input clock input, the OSF bit is set to 1 in the timer status register (TSR) when
the next DCNT input clock pulse is input (when underflow occurs). However, when DCNT is
H'0000, it remains unchanged at H'0000 no matter how many DCNT input clock pulses are input.
The timing in this case is shown in figure 10.33.
CK
DCNT input clock
DCNT H'0001
H'0000
H'0000
Underflow signal
Interrupt status flag
OSF
Interrupt request signal
OSI
Figure 10.33 OSF Setting Timing in Underflow
Rev. 5.00 Jan 06, 2006 page 309 of 818
REJ09B0273-0500