SH7050 Datasheet, PDF (491/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 15 Compare Match Timer (CMT)
15.5.3 Contention between CMCNT Byte Write and Incrementation
If an increment occurs during the T₂ state of the CMCNT byte write cycle, the counter write has
priority, so no increment of the write data results on the writing side. The byte data on the side not
performing the writing is also not incremented, so the contents are those before the write.
Figure 15.8 shows the timing when an increment occurs during the T₂ state of the CMCNTH write
cycle.
CMCNT write cycle
T₁
T₂
CK
Address
CMCNTH
Internal
write signal
CMCNT
input clock
CMCNTH
N
CMCNTL
X
M
CMCNTH write data
X
Figure 15.8 CMCNT Byte Write and Increment Contention
Rev. 5.00 Jan 06, 2006 page 471 of 818
REJ09B0273-0500