SH7050 Datasheet, PDF (538/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 17 I/O Ports (I/O)
17.2.1 Register Configuration
The port A register is shown in table 17.1.
Table 17.1 Port A Register
Name
Abbreviation R/W Initial Value Address
Port A data register
PADR
R/W H'0000
H'FFFF8380
Note: A register access is performed in two cycles regardless of the access size.
Access Size
8, 16
17.2.2 Port A Data Register (PADR)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
DR DR DR DR DR DR DR DR DR DR DR DR DR DR DR DR
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
The port A data register (PADR) is a 16-bit readable/writable register that stores port A data. Bits
PA15DR to PA0DR correspond to pins PA15/A15 to PA0/A0.
When a pin functions as a general output, if a value is written to PADR, that value is output
directly from the pin, and if PADR is read, the register value is returned directly regardless of the
pin state. When the POD pin is driven low, general outputs go to the high-impedance state
regardless of the PADR value. When the POD pin is driven high, the written value is output from
the pin.
When a pin functions as a general input, if PADR is read the pin state, not the register value, is
returned directly. If a value is written to PADR, although that value is written into PADR it does
not affect the pin state. Table 17.2 summarizes port A data register read/write operations.
PADR is initialized by a power-on reset (excluding a WDT power-on reset), and in hardware
standby mode. It is not initialized in software standby mode or sleep mode.
Rev. 5.00 Jan 06, 2006 page 518 of 818
REJ09B0273-0500