SH7050 Datasheet, PDF (3/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Preface
The SH7050 series (SH7050, SH7051) is a single-chip RISC microcontroller that integrates a
RISC CPU core using an original Renesas architecture with peripheral functions required for
system configuration.
The CPU has a RISC-type instruction set. Most instructions can be executed in one state (one
system clock cycle), which greatly improves instruction execution speed. In addition, the 32-bit
internal architecture enhances data processing power. With this CPU, it has become possible to
assemble low-cost, high-performance/high-functionality systems even for applications such as
real-time control, which could not previously be handled by microcontrollers because of their
high-speed processing requirements.
In addition, the SH7050 series includes on-chip peripheral functions necessary for synchronous
configuration, such as large-capacity ROM and RAM, a direct memory access controller
(DMAC), timers, a serial communication interface (SCI), A/D converter, interrupt controller
(INTC), and I/O ports.
ROM and SRAM can be directly connected by means of an external memory access support
function, greatly reducing system cost.
There are versions of on-chip ROM: mask ROM and flash memory. The flash memory can be
programmed with a programmer that supports SH7050 series programming, and can also be
programmed and erased by software.
This hardware manual describes the SH7050 series hardware. Refer to the programming manual
for a detailed description of the instruction set.
Related Manual
SH7050 series instructions
SH-1/SH-2/SH-DSP Software Manual (Document No. REJ09B0171-0500O)
Please consult your Renesas sales representative for details of development environment system.
Rev. 5.00 Jan 06, 2006 page iii of xx