SH7050 Datasheet, PDF (229/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
10.1.4 Prescaler Diagram
Figure 10.10 shows the first and second prescaler stages in the ATU. The output of the first
prescaler stage is input to channel 0. Either the output of the second prescaler stage or an external
clock can be input to channels 1 to 10, and an additional external clock (TCLKA or TCLKB) can
be input to channels 1 to 5.
φ/m (1 ≤ m ≤ 32) can be set as the output of the first prescaler stage (φ'), the setting being made in
prescaler control register 1 (PSCR1).
φ/2ⁿ (0 ≤ n ≤ 5) can be set as the output of the second prescaler stage (φ"), the setting being made
in the timer control register (TCR).
Input clock
φ
First prescaler
stage setting
register
PSCR1
φ' = ø/m
1 ≤ m ≤ 32
Second prescaler
stage setting
register
φ'
Channel 0
TCR1
TCR2
TCR3
TCR4
TCR5
φ" or
external clock
φ" or
external clock
φ" or
external clock
φ" or
external clock
φ" or
external clock
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Settable prescaler values
φ' = φ/m (1 ≤ m ≤ 32)
φ" = φ'/2ⁿ (0 ≤ n ≤ 5)
or external clock
φ" = φ'/2ⁿ (0 ≤ n ≤ 5)
TCR6
φ"
TCR7
φ"
TCR8
φ"
TCR9
φ"
TCR10
φ"
Channel 6
Channel 7
Channel 8
Channel 9
Channel 10
DCNT10A–DCNT10F
Channel 10
DCNT10G, DCNT10H
Figure 10.10 Prescaler Diagram
Rev. 5.00 Jan 06, 2006 page 209 of 818
REJ09B0273-0500