SH7050 Datasheet, PDF (826/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Appendix A On-Chip Supporting Module Registers
Bit
13, 12
11–8
6
5
4, 3
2
Bit Name
Value
Description
Source address mode 0 0
1 and 0 (SM1, SM0)
1
Source address fixed
(Initial value)
Source address incremented (+1 for 8-bit transfer, +2 for 16-bit
transfer, +4 for 32-bit transfer)
10
Source address decremented (–1 for 8-bit transfer, –2 for 16-bit
transfer, –4 for 32-bit transfer)
1
Setting prohibited
Resource select
0 0 0 0 External request, dual address mode
3, 2, 1, and 0
(RS3, RS2, RS1, RS0)
1 Setting prohibited
(Initial value)
1 0 External request, single address mode
External address space to external device
1 External request, single address mode
External device to external address space
1 0 0 Auto-request
1 Setting prohibited
1 0 ATU, compare match 6 (CMI6)
1 ATU, input capture 0B (ICI0B)
1 0 0 0 SCI0 transmission
1 SCI0 reception
1 0 SCI1 transmission
1 SCI1 reception
1 0 0 SCI2 transmission
1 SCI2 reception
1 0 On-chip A/D0
1 On-chip A/D1
DREQ select (DS)
0
Low level detection
(Initial value)
1
Falling edge detection
Transmit mode (TM) 0
Cycle steal mode
1
Burst mode
Transmit size 1 and 0
(TS1, TS0)
00
1
Byte size (8 bits)
Word size (16 bits)
(Initial value)
10
Longword size (32 bits)
1
Setting prohibited
Interrupt enable (IE) 0
No interrupt request generated at end of number of transfers specified
in DMATCR
(Initial value)
1
Interrupt request generated at end of number of transfers specified in
DMATCR
Rev. 5.00 Jan 06, 2006 page 806 of 818
REJ09B0273-0500