SH7050 Datasheet, PDF (10/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

8.1.4 Register Configuration......................................................................................... 111
8.1.5 Address Map ........................................................................................................ 112
8.2 Description of Registers.................................................................................................... 115
8.2.1 Bus Control Register 1 (BCR1) ........................................................................... 115
8.2.2 Bus Control Register 2 (BCR2) ........................................................................... 116
8.2.3 Wait Control Register 1 (WCR1)......................................................................... 119
8.2.4 Wait Control Register 2 (WCR2)......................................................................... 121
8.2.5 RAM Emulation Register (RAMER)................................................................... 122
8.3 Accessing Ordinary Space ................................................................................................ 124
8.3.1 Basic Timing........................................................................................................ 124
8.3.2 Wait State Control................................................................................................ 125
8.3.3 CS Assert Period Extension ................................................................................. 127
8.4 Waits between Access Cycles ........................................................................................... 128
8.4.1 Prevention of Data Bus Conflicts......................................................................... 128
8.4.2 Simplification of Bus Cycle Start Detection ........................................................ 130
8.5 Bus Arbitration.................................................................................................................. 131
8.6 Memory Connection Examples......................................................................................... 132
Section 9 Direct Memory Access Controller (DMAC) ............................................ 135
9.1 Overview........................................................................................................................... 135
9.1.1 Features................................................................................................................ 135
9.1.2 Block Diagram ..................................................................................................... 137
9.1.3 Pin Configuration................................................................................................. 138
9.1.4 Register Configuration......................................................................................... 138
9.2 Register Descriptions ........................................................................................................ 140
9.2.1 DMA Source Address Registers 0–3 (SAR0–SAR3) .......................................... 140
9.2.2 DMA Destination Address Registers 0–3 (DAR0–DAR3).................................. 141
9.2.3 DMA Transfer Count Registers 0–3 (DMATCR0–DMATCR3)......................... 142
9.2.4 DMA Channel Control Registers 0–3 (CHCR0–CHCR3)................................... 143
9.2.5 DMAC Operation Register (DMAOR) ................................................................ 148
9.3 Operation .......................................................................................................................... 150
9.3.1 DMA Transfer Flow ............................................................................................ 150
9.3.2 DMA Transfer Requests ...................................................................................... 152
9.3.3 Channel Priority ................................................................................................... 155
9.3.4 DMA Transfer Types........................................................................................... 158
9.3.5 Address Modes .................................................................................................... 159
9.3.6 Dual Address Mode ............................................................................................. 160
9.3.7 Bus Modes ........................................................................................................... 167
9.3.8 Relationship between Request Modes and Bus Modes by DMA Transfer
Category............................................................................................................... 168
9.3.9 Bus Mode and Channel Priority Order................................................................. 169
Rev. 5.00 Jan 06, 2006 page x of xx