SH7050 Datasheet, PDF (108/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 6 Interrupt Controller (INTC)
Bits 7 to 0—IRQ0–IRQ7 Flags (IRQ0F–IRQ7F): These bits display the IRQ0–IRQ7 interrupt
request status.
Bits 7-0:
IRQ0F–IRQ7F
0
1
Detection Setting
Level detection
Edge detection
Level detection
Edge detection
Description
No IRQn interrupt request exists.
Clear conditions: When IRQn input is high level
No IRQn interrupt request was detected. (initial value)
Clear conditions:
1. When a 0 is written after reading IRQnF = 1 status
2. When IRQn interrupt exception processing has been
executed
An IRQn interrupt request exists.
Set conditions: When IRQn input is low level
An IRQn interrupt request was detected.
Set conditions: When a falling edge occurs at an IRQn
input
IRQnS
(0: level, 1: edge)
ISR.IRQnF
IRQ pin
level
detection
edge
detection
SQ
CPU
interrupt
request
RESIRQn
R
(IRQn interrupt reception/writing a 0 to IRQnF after reading an IRQnF = 1)
Figure 6.2 IRQ0 – IRQ7 Interrupt Control
Rev. 5.00 Jan 06, 2006 page 88 of 818
REJ09B0273-0500