SH7050 Datasheet, PDF (236/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
10.2 Register Descriptions
10.2.1 Timer Start Register (TSTR)
The timer start register (TSTR) is a 16-bit register. The ATU has one TSTR register.
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
— — — — — — STR9 STR8 STR7 STR6 STR5 STR4 STR3 STR2 STR1 STR0
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TSTR is a 16-bit readable/writable register that starts and stops the free-running counter (TCNT)
in channels 0 to 9.
TSTR is initialized to H'0000 by a power-on reset, and in hardware standby mode and software
standby mode.
Bits 15 to 10—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 9—Counter Start 9 (STR9): Starts and stops free-running counter 9 (TCNT9).
Bit 9:
STR7
0
1
Description
TCNT9 is halted
TCNT9 counts
(Initial value)
Bit 8—Counter Start 8 (STR8): Starts and stops free-running counter 8 (TCNT8).
Bit 8:
STR8
0
1
Description
TCNT8 is halted
TCNT8 counts
(Initial value)
Rev. 5.00 Jan 06, 2006 page 216 of 818
REJ09B0273-0500