SH7050 Datasheet, PDF (190/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 9 Direct Memory Access Controller (DMAC)
continuously from the second bus cycle. The dummy cycle is not counted in the number of
transfer cycles, so there is no need to recognize the dummy cycle when setting the TCR.
DREQ sampling from the second time begins from the start of the transfer one bus cycle prior to
the DMAC transfer generated by the previous sampling.
DRAK is output once for the first DREQ sampling, irrespective of transfer mode or DREQ
detection method. In burst mode, using edge detection, DREQ is sampled for the first cycle only,
so DRAK is also output for the first cycle only. Therefore, the DREQ signal negate timing can be
ascertained, and this facilitates handshake operations of transfer requests with the DMAC.
Cycle Steal Mode Operations: In cycle steal mode, DREQ sampling timing is the same
irrespective of dual or single address mode, or whether edge or low-level DREQ detection is used.
For example, DMAC transfer begins (figure 9.15), at the earliest, three cycles from the first
sampling timing. The second sampling begins at the start of the transfer one bus cycle prior to the
start of the DMAC transfer initiated by the first sampling (i.e., from the start of the CPU(3)
transfer). At this point, if DREQ detection has not occurred, sampling is executed every cycle
thereafter.
As in figure 9.16, whatever cycle the CPU transfer cycle is, the next sampling begins from the
start of the transfer one bus cycle before the DMAC transfer begins.
Figure 9.15 shows an example of output during DACK read and figure 9.16 an example of output
during DACK write.
Rev. 5.00 Jan 06, 2006 page 170 of 818
REJ09B0273-0500