SH7050 Datasheet, PDF (242/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
Timer Control Registers 1 to 5 (TCR1 to TCR5)
Bit: 7
—
Initial value: 0
R/W: R
6
5
4
3
2
1
0
— CKEG1 CKEG0 — CKSEL2 CKSEL1 CKSEL0
0
0
0
0
0
0
0
R
R/W R/W
R
R/W R/W R/W
Bits 7 and 6—Reserved: These bits are always read as 0, and should only be written with 0.
Bits 5 and 4—Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select external clock input
edges when an external clock is used.
Bit 5:
CKEG1
0
1
Bit 4:
CKEG0
0
1
0
1
Description
Rising edges counted
Falling edges counted
Both rising and falling edges counted
External clock count disabled
(Initial value)
Bit 3—Reserved: This bit is always read as 0, and should only be written with 0.
Bits 2 to 0—Clock Select 2 to 0 (CKSEL2 to CKSEL0): These bits select whether an internal
clock or external clock is used.
When an internal clock is selected, scaled clock φ" is selected from φ', φ'/2, φ'/4, φ'/8, φ'/16, and
φ'/32.
When an external clock is selected, either TCLKA or TCLKB is selected.
Rev. 5.00 Jan 06, 2006 page 222 of 818
REJ09B0273-0500