SH7050 Datasheet, PDF (259/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
Bit 0—Input Capture Flag (ICF0A): Status flag that indicates ICR0A input capture.
Bit 0:
ICF0A
0
1
Description
[Clearing condition]
(Initial value)
When ICF0A is read while set to 1, then 0 is written in ICF0A
[Setting condition]
When the TCNT0 value is transferred to the input capture register (ICR0A) by an input
capture signal
Timer Status Register B (TSRB)
TSRB indicates the status of channel 1 input capture, compare-match, and overflow.
Bit: 7
6
5
4
—
OVF1 IMF1F IMF1E
Initial value: 0
0
0
0
R/W: R R/(W)* R/(W)* R/(W)*
Note: * Only 0 can be written, to clear the flag.
3
IMF1D
0
R/(W)*
2
IMF1C
0
R/(W)*
1
IMF1B
0
R/(W)*
0
IMF1A
0
R/(W)*
Bit 7—Reserved: This bit is always read as 0, and should only be written with 0.
Bit 6—Overflow Flag (OVF1): Status flag that indicates TCNT1 overflow.
Bit 6:
OVF1
0
1
Description
[Clearing condition])
When OVF1 is read while set to 1, then 0 is written in OVF1
[Setting condition]
When the TCNT1 value overflows (from H'FFFF to H'0000)
(Initial value)
Rev. 5.00 Jan 06, 2006 page 239 of 818
REJ09B0273-0500