SH7050 Datasheet, PDF (273/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
Timer Interrupt Enable Register A (TIERA)
TIERA controls enabling/disabling of channel 0 input capture and overflow interrupt requests.
Bit: 7
6
5
4
3
2
1
0
—
—
— OVE0 ICE0D ICE0C ICE0B ICE0A
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R/W R/W R/W R/W R/W
Bits 7 to 5—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 4—Overflow Interrupt Enable (OVE0): Enables or disables OVI0 requests when the
overflow flag (OVF0) in TSR is set to 1.
Bit 4:
OVE0
0
1
Description
OVI0 interrupt requested by OVF0 is disabled
OVI0 interrupt requested by OVF0 is enabled
(Initial value)
Bit 3—Input Capture Interrupt Enable (ICE0D): Enables or disables ICI0D requests when the
input capture flag (ICF0D) in TSR is set to 1.
Bit 3:
ICE0D
0
1
Description
ICI0D interrupt requested by ICF0D is disabled
ICI0D interrupt requested by ICF0D is enabled
(Initial value)
Bit 2—Input Capture Interrupt Enable (ICE0C): Enables or disables ICI0C requests when the
input capture flag (ICF0C) in TSR is set to 1.
Bit 2:
ICE0C
0
1
Description
ICI0C interrupt requested by ICF0C is disabled
ICI0C interrupt requested by ICF0C is enabled
(Initial value)
Rev. 5.00 Jan 06, 2006 page 253 of 818
REJ09B0273-0500