SH7050 Datasheet, PDF (465/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 14 A/D Converter
Bits 1 and 0—Channel Select 1 and 0 (CH1 and CH0): These bits, together with the SCAN bit,
select the analog input channels.
To prevent incorrect operation, ensure that the ADST bit in A/D control/status register 1
(ADCSR1) is cleared to 0 before changing the analog input channel selection.
Bit 1:
CH3
0
1
Bit 0:
CH0
0
1
0
1
Analog Input Channels
Single Mode
Scan Mode
AN12 (Initial value)
AN12
AN13
AN12, 13
AN14
AN12–14
AN15
AN12–15
14.2.5 A/D Control Register 1 (ADCR1)
A/D control register 1 (ADCR1) is an 8-bit readable/writable register that controls the start of A/D
conversion and selects the operating clock.
ADCR1 is initialized to H'7F by a power-on reset, and in hardware standby mode and software
standby mode.
Bit: 7
6
5
4
3
2
1
0
TRGE —
—
—
—
—
—
—
Initial value: 0
1
1
1
1
1
1
1
R/W: R/W
R
R
R
R
R
R
R
Bit 7—Trigger Enable (TRGE): Same as TRGE in ADCR0.
Bits 6 to 0—Reserved: These bits are always read as 1, and should only be written with 1.
Rev. 5.00 Jan 06, 2006 page 445 of 818
REJ09B0273-0500