SH7050 Datasheet, PDF (825/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Appendix A On-Chip Supporting Module Registers
DMA Channel Control Registers 0 to 3
(CHCR0 to CHCR3)
H'FFFF86CC (Channel 0) 16/32
H'FFFF86DC (Channel 1) 16/32
H'FFFF86EC (Channel 2) 16/32
H'FFFF86FC (Channel 3) 16/32
DMAC
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Bit name: — — — — — — — — — — — DI RO RL AM AL
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R R R R R R R R R R R R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit name: DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0 — DS TM TS1 TS0 IE TE DE
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/(W) R/W
Notes: 1. Only 0 can be written in the TE bit, after reading 1 from this bit.
2. The DI, RO, RL, AM, AL, or DS bit may be absent, depending on the channel.
Bit
20
19
18
17
16
15, 14
Bit Name
Value
Direct/indirect select 0
(DI)
1
Source address reload 0
(RO)
1
Request check level 0
(RL)
1
Acknowledge mode
0
(AM)
1
Acknowledge level
0
(AL)
1
Destination address
mode 1 and 0
(DM1, DM0)
00
1
10
1
Description
Channel 3 operates in direct address mode
Channel 3 operates in indirect address mode
Source address not reloaded
(Initial value)
(Initial value)
Source address reloaded
Active-high DRAK output
(Initial value)
Active-low DRAK output
DACK output in read cycle
(Initial value)
DACK output in write cycle
Active-high output
(Initial value)
Active-low output
Destination address fixed
(Initial value)
Destination address incremented (+1 for 8-bit transfer, +2 for 16-bit
transfer, +4 for 32-bit transfer)
Destination address decremented (–1 for 8-bit transfer, –2 for 16-bit
transfer, –4 for 32-bit transfer)
Setting prohibited
Rev. 5.00 Jan 06, 2006 page 805 of 818
REJ09B0273-0500