SH7050 Datasheet, PDF (717/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Appendix A On-Chip Supporting Module Registers
Serial Status Register (SSR)
H'FFFF81A4 (Channel 0) 8/16
SCI
H'FFFF81B4 (Channel 1)
H'FFFF81C4 (Channel 2)
Bit: 7
6
5
4
Bit name: TDRE RDRF ORER FER
Initial value: 1
0
0
0
R/W: R/(W)* R/(W)* R/(W)* R/(W)*
Note: * Only 0 can be written to clear the flag.
3
PER
0
R/(W)*
2
TEND
1
R
1
MPB
0
R
0
MPBT
0
R/W
Bit Bit Name
7 Transmit data
register empty
(TDRE)
6 Receive data
register full
(RDRF)
5 Overrun error
(ORER)
Value Description
0
Valid transmit data has been written in TDR.
[Clearing conditions]
1. Read TDRE when TDRE = 1, then write 0 in TDRE
2. The DMAC writes data in TDR
1
There is no valid transmit data in TDR
(Initial value)
[Setting conditions]
1. Power-on reset, or transition to hardware standby mode or software
standby mode
2. TE is cleared to 0 in SCR
3. Data is transferred from TDR to TSR, enabling new data to be written
in TDR
0
There is no valid receive data in RDR
(Initial value)
[Clearing conditions]
1. Power-on reset, or transition to hardware standby mode or software
standby mode
2. Read RDRF when RDRF = 1, then write 0 in RDRF
3. The DMAC reads data from RDR
1
There is valid receive data in RDR
[Setting condition]
Serial data is received normally and transferred from RSR to RDR
0
Receiving in progress, or completed normally
(Initial value)
[Clearing conditions]
1. Power-on reset, or transition to hardware standby mode or software
standby mode
2. Read ORER when ORER = 1, then write 0 in ORER
1
Overrun error occurred during reception
[Setting condition]
Overrun error (reception of next serial data ends while RDRF = 1)
Rev. 5.00 Jan 06, 2006 page 697 of 818
REJ09B0273-0500