SH7050 Datasheet, PDF (812/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Appendix A On-Chip Supporting Module Registers
Timer Control/Status Register (TCSR)
H'FFFF8610
8
WDT
Bit: 7
6
5
4
3
2
1
0
Bit name: OVF WT/IT TME
—
—
CKS2 CKS1 CKS0
Initial value: 0
0
0
1
1
0
0
0
R/W: R/(W)* R/W R/W
R
R
R/W R/W R/W
Note: * To prevent TCSR from being modified easily, the write method differs from that used for
general registers. For details, see section 12.2.4, Register Access.
Bit
Bit Name
Value
Description
7
Overflow flag (OVF) 0
No TCNT overflow in interval timer mode
(Initial value)
[Clearing condition]
Read OVF, then write 0 in OVF
1
TCNT overflow in interval timer mode
6
Timer mode select
0
(WT/IT)
Interval timer mode: Interval timer interrupt (ITI)
request sent to CPU when TCNT overflows
(Initial value)
1
Watchdog timer mode: WDTOVF signal output
externally when TCNT overflows
5
Timer enable (TME) 0
Timer disabled: TCNT is initialized to H'00 and
halted
(Initial value)
1
Timer enabled: TCNT starts counting
WDTOVF signal or interrupt generated when
TCNT overflows
Clock
Overflow Interval^*
(When φ = 20 MHz)
2–0
Clock select 2 to 0
0 0 0 φ/2 (Initial value)
(CKS2 to CKS0)
1 φ/64
25.6 µs
819.2 µs
1 0 φ/128
1.6 ms
1 φ/256
3.3 ms
1 0 0 φ/512
6.6 ms
1 φ/1024
13.1 ms
1 0 φ/4096
52.4 ms
1 φ/8192
104.9 ms
Note: * The overflow interval listed is the time from when the TCNT begins counting at H'00
until an overflow occurs.
Rev. 5.00 Jan 06, 2006 page 792 of 818
REJ09B0273-0500