SH7050 Datasheet, PDF (806/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Appendix A On-Chip Supporting Module Registers
A/D Control Register 0 (ADCR0)
H'FFFF85E9
Bit: 7
6
5
4
3
Bit name: TRGE CKS ADST —
—
Initial value: 0
0
0
1
1
R/W: R/W R/W R/W
R
R
8/16
2
1
—
—
1
1
R
R
A/D
0
—
1
R
Bit
Bit Name
Value Description
7
Trigger enable
0
Starting of A/D conversion by external trigger or ATU
(TRGE)
trigger is disabled
(Initial value)
1
Starting of A/D conversion by external trigger or ATU
trigger is enabled
6
Clock select (CKS) 0
Conversion time = 266 states (maximum) (Initial value)
1
Conversion time = 134 states (maximum)
5
A/D start (ADST) 0
A/D conversion is stopped
(Initial value)
1
A/D conversion is in progress
[Clearing conditions]
1. Single mode: ADST is cleared automatically when
A/D conversion ends
2. Scan mode: Confirm that ADF in ADCSR0 is 1, then
write 0 in ADST
Rev. 5.00 Jan 06, 2006 page 786 of 818
REJ09B0273-0500