SH7050 Datasheet, PDF (204/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 9 Direct Memory Access Controller (DMAC)
Burst Mode, Single Address, and Edge Detection: In burst mode with single address and edge
detection, DREQ sampling is conducted only on the first cycle. In figure 9.24, a dummy cycle is
inserted, at the earliest, three cycles after the timing for the first sampling. During this period, data
is undefined, and DACK is not output. Nor is the number of DMAC transfers counted. Thereafter,
DMAC transfer continues until the data transfer count set in the TCR has ended. DREQ sampling
is not conducted during this period. Therefore, DRAK is output on the first cycle only.
When DMAC transfer is resumed after being halted by a NMI or address error, be sure to reinput
an edge request. DRAK is output once, and the remaining transfer restarts after output of one
dummy cycle.
The DACK output period in burst mode is the same as in cycle steal mode.
Rev. 5.00 Jan 06, 2006 page 184 of 818
REJ09B0273-0500