SH7050 Datasheet, PDF (395/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 13 Serial Communication Interface (SCI)
13.2.5 Serial Mode Register (SMR)
The serial mode register (SMR) is an 8-bit register that specifies the SCI serial communication
format and selects the clock source for the baud rate generator.
The CPU can always read and write the SMR. The SMR is initialized to H'00 by a power-on reset,
in hardware standby mode and software standby mode.
Bit: 7
6
5
4
3
2
1
0
C/A CHR
PE
O/E STOP MP CKS1 CKS0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit 7—Communication Mode (C/A): Selects whether the SCI operates in the asynchronous or
clock synchronous mode.
Bit 7: C/A
0
1
Description
Asynchronous mode (initial value)
Clocked synchronous mode
Bit 6—Character Length (CHR): Selects 7-bit or 8-bit data in the asynchronous mode. In the
clock synchronous mode, the data length is always eight bits, regardless of the CHR setting.
Bit 6: CHR
0
1
Description
Eight-bit data (initial value)
Seven-bit data. (When 7-bit data is selected, the MSB (bit 7) of the
transmit data register is not transmitted.)
Bit 5—Parity Enable (PE): Selects whether to add a parity bit to transmit data and to check the
parity of receive data, in the asynchronous mode. In the clock synchronous mode, a parity bit is
neither added nor checked, regardless of the PE setting.
Bit 5: PE
0
1
Description
Parity bit not added or checked (initial value)
Parity bit added and checked. When PE is set to 1, an even or odd
parity bit is added to transmit data, depending on the parity mode (O/E)
setting. Receive data parity is checked according to the even/odd (O/E)
mode setting.
Rev. 5.00 Jan 06, 2006 page 375 of 818
REJ09B0273-0500