SH7050 Datasheet, PDF (228/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
10.1.3 Inter-Channel and Inter-Module Signal Connection Diagram
Channel 10.9 shows the connections between channels and between modules in the ATU.
DMAC activation
(input capture)
Channel 0
Internal CLK
TCNT0
TCNT0H TCNT0L
TIA0
TIB0
TIC0
TID0
ICR0AH
ICR0BH
ICR0CH
ICR0DH
ICR0AL
ICR0BL
ICR0CL
ICR0DL
TRG0A
Trigger output
(synchronous capture)
A/D converter activation
(“1” detection)
Channel 1
Internal CLK
TCLKA
TCLKB
TCNT1
TIOA1
TIOB1
TIOC1
TIOD1
TIOE1
TIOF1
Trigger input
GR1A
GR1B
GR1C
GR1D
GR1E
GR1F
OSBR
Internal CLK
TCLKA
TCLKB
TCNT2
Channel 2
TIOA2
TIOB2
GR2A
GR2B
TRG1A
Internal CLK
TCNT6
TO6
Channel 6
Compare-match signal
transmission to advanced
pulse controller (APC)
CYLR6
DTR6
BFR6
DMAC
activation
(compare-
match)
Trigger output
(compare-match)
Channel 10
TOA10
TOB10
TOC10
TOD10
TOE10
TOF10
TOG10
TOH10
Offset compare-
match signal
Down-counters
DCNT10A
OFF1A
DCNT10B
OFF1B
DCNT10C
DCNT10D
DCNT10E
OFF1C
OFF1D
OFF1E
DCNT10F
OFF1F
DCNT10G
OFF2A
DCNT10H
OFF2B
Figure 10.9 Inter-Channel and Inter-Module Signal Connection Diagram
Rev. 5.00 Jan 06, 2006 page 208 of 818
REJ09B0273-0500