SH7050 Datasheet, PDF (9/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

6.2.5 Interrupt Exception Vectors and Priority Rankings ............................................. 79
6.3 Description of Registers.................................................................................................... 84
6.3.1 Interrupt Priority Registers A–H (IPRA–IPRH) .................................................. 84
6.3.2 Interrupt Control Register (ICR).......................................................................... 86
6.3.3 IRQ Status Register (ISR).................................................................................... 87
6.4 Interrupt Operation............................................................................................................ 89
6.4.1 Interrupt Sequence ............................................................................................... 89
6.4.2 Stack after Interrupt Exception Processing .......................................................... 91
6.5 Interrupt Response Time................................................................................................... 92
6.6 Data Transfer with Interrupt Request Signals ................................................................... 93
6.6.1 Handling CPU Interrupt Sources, but Not DMAC Activating Sources ............... 94
6.6.2 Handling DMAC Activating Sources but Not CPU Interrupt Sources ................ 94
Section 7 User Break Controller (UBC) ....................................................................... 95
7.1 Overview........................................................................................................................... 95
7.1.1 Features................................................................................................................ 95
7.1.2 Block Diagram ..................................................................................................... 96
7.1.3 Register Configuration......................................................................................... 97
7.2 Register Descriptions ........................................................................................................ 97
7.2.1 User Break Address Register (UBAR) ................................................................ 97
7.2.2 User Break Address Mask Register (UBAMR) ................................................... 98
7.2.3 User Break Bus Cycle Register (UBBR) ............................................................. 100
7.3 Operation .......................................................................................................................... 102
7.3.1 Flow of the User Break Operation ....................................................................... 102
7.3.2 Break on On-Chip Memory Instruction Fetch Cycle ........................................... 104
7.3.3 Program Counter (PC) Values Saved................................................................... 104
7.4 Use Examples.................................................................................................................... 105
7.4.1 Break on CPU Instruction Fetch Cycle................................................................ 105
7.4.2 Break on CPU Data Access Cycle ....................................................................... 106
7.4.3 Break on DMA/DTC Cycle ................................................................................. 106
7.5 Cautions on Use ................................................................................................................ 107
7.5.1 On-Chip Memory Instruction Fetch..................................................................... 107
7.5.2 Instruction Fetch at Branches............................................................................... 107
7.5.3 Contention between User Break and Exception Handling................................... 108
7.5.4 Break at Non-Delay Branch Instruction Jump Destination.................................. 108
Section 8 Bus State Controller (BSC) ........................................................................... 109
8.1 Overview........................................................................................................................... 109
8.1.1 Features................................................................................................................ 109
8.1.2 Block Diagram ..................................................................................................... 110
8.1.3 Pin Configuration................................................................................................. 111
Rev. 5.00 Jan 06, 2006 page ix of xx