SH7050 Datasheet, PDF (335/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
10.5.3 8-Bit or 16-Bit Accessible Registers
The timer control register (TCR), timer I/O control registers 1 to 5 (TIOR1 to TIOR5), and the
timer connection register (TCNR) are 8-bit registers. These registers are connected to the upper 8
bits or lower 8 bits of the internal 16-bit data bus, and can be read or written a byte at a time.
In addition, a pair of 8-bit registers for which only the least significant bit of the address is
different, such as timer I/O control register 4A (TIOR4A) and timer I/O control register 4B
(TIOR4B), can be read or written in combination a word at a time.
Figures 10.40 and 10.41 show the operation when performing individual byte read or write
accesses to TIOR4A and TIOR4B. Figure 10.42 shows the operation when performing a word
read or write access to TIOR4A and TIOR4B simultaneously.
CPU
Internal data bus
Only upper 8 bits used
Bus
interface
Module data bus
Only upper 8 bits used
Figure 10.40 Byte Read/Write Access to TIOR4A
TIOR4A
TIOR4B
CPU
Internal data bus
Only lower 8 bits used
Bus
interface
Module data bus
Only lower 8 bits used
Figure 10.41 Byte Read/Write Access to TIOR4B
TIOR4A
TIOR4B
CPU
Internal data bus
Bus
interface
Module data bus
TIOR4A
TIOR4B
Figure 10.42 Word Read/Write Access to TIOR4A and TIOR4B
Rev. 5.00 Jan 06, 2006 page 315 of 818
REJ09B0273-0500