SH7050 Datasheet, PDF (669/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 21 Power-Down State
21.4.2 Canceling the Software Standby Mode
The standby mode is canceled by an NMI interrupt, a power-on reset, or a manual reset.
Cancellation by an NMI: Clock oscillation starts when a rising edge or falling edge (selected by
the NMI edge select bit (NMIE) of the interrupt control register (ICR) of the INTC) is detected in
the NMI signal. This clock is supplied only to the watchdog timer. A WDT overflow occurs if the
time established by the clock select bits (CKS2–CKS0) in the TCSR of the WDT elapses before
transition to the standby mode. The occurrence of this overflow is used to indicate that the clock
has stabilized, so the clock is supplied to the entire chip, the standby mode is canceled, and NMI
exception processing begins.
When canceling standby mode with NMI interrupts, set the CKS2–CKS0 bits so that the WDT
overflow period is longer than the oscillation stabilization time.
When canceling standby mode with an NMI pin set for falling edge, be sure that the NMI pin level
upon entering standby (when the clock is halted) is high level, and that the NMI pin level upon
returning from standby (when the clock starts after oscillation stabilization) is low level. When
canceling standby mode with an NMI pin set for rising edge, be sure that the NMI pin level upon
entering standby (when the clock is halted) is low level, and that the NMI pin level upon returning
from standby (when the clock starts after oscillation stabilization) is high level.
Cancellation by a Power-On Reset: A power-on reset caused by setting the RES pin to low level
cancels the standby mode.
Rev. 5.00 Jan 06, 2006 page 649 of 818
REJ09B0273-0500