SH7050 Datasheet, PDF (385/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 12 Watchdog Timer (WDT)
12.3.4 Timing of Setting the Overflow Flag (OVF)
In the interval timer mode, when the TCNT overflows, the OVF flag of the TCSR is set to 1 and
an interval timer interrupt is simultaneously requested (figure 12.6).
CK
TCNT
H'FF H'00
Overflow signal
(internal signal)
OVF
Figure 12.6 Timing of Setting the OVF
12.3.5 Timing of Setting the Watchdog Timer Overflow Flag (WOVF)
When the TCNT overflows in the watchdog timer mode, the WOVF bit of the RSTCSR is set to 1
and a WDTOVF signal is output. When the RSTE bit is set to 1, TCNT overflow enables an
internal reset signal to be generated for the entire chip (figure 12.7).
CK
TCNT
Overflow signal
(internal signal)
H'FF H'00
WOVF
Figure 12.7 Timing of Setting the WOVF Bit
Rev. 5.00 Jan 06, 2006 page 365 of 818
REJ09B0273-0500