SH7050 Datasheet, PDF (382/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 12 Watchdog Timer (WDT)
Writing 0 to the WOVF bit
15
87
0
Address: H'FFFF8612
H'A5
H'00
Writing to the RSTE bit
15
Address: H'FFFF8612
H'5A
87
0
Write data
Figure 12.3 Writing to the RSTCSR
Reading from the TCNT, TCSR, and RSTCSR: TCNT, TCSR, and RSTCSR are read like
other registers. Use byte transfer instructions. The read addresses are H'FFFF8610 for the TCSR,
H'FFFF8611 for the TCNT, and H'FFFF8613 for the RSTCSR.
12.3 Operation
12.3.1 Watchdog Timer Mode
To use the WDT as a watchdog timer, set the WT/IT and TME bits of the TCSR to 1. Software
must prevent TCNT overflow by rewriting the TCNT value (normally by writing H'00) before
overflow occurs. No TCNT overflows will occur while the system is operating normally, but if the
TCNT fails to be rewritten and overflows occur due to a system crash or the like, a WDTOVF
signal is output externally (figure 12.4). The WDTOVF signal can be used to reset the system. The
WDTOVF signal is output for 128 φ clock cycles.
If the RSTE bit in the RSTCSR is set to 1, a signal to reset the chip will be generated internally
simultaneous to the WDTOVF signal when TCNT overflows. Either a power-on reset or a manual
reset can be selected by the RSTS bit. The internal reset signal is output for 512 φ clock cycles.
When a watchdog overflow reset is generated simultaneously with a reset input at the RES pin, the
RES reset takes priority, and the WOVF bit is cleared to 0.
The following are not initialized a WDT reset signal:
• PFC (Pin Function Controller) function register
• I/O port register
Initializing is only possible by external power-on reset.
Rev. 5.00 Jan 06, 2006 page 362 of 818
REJ09B0273-0500