SH7050 Datasheet, PDF (224/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
Block Diagram of Channels 3 and 4: Figure 10.5 shows a block diagram of ATU channels 3 and
4.
TSTR
TCLKA
TCLKB
φ/(m·2ⁿ)
1 ≤ m ≤ 32
0≤n≤5
Clock selection
Comparator
Control logic
OVI3/4
IMI3A/4A
IMI3B/4B
IMI3C/4C
IMI3D/4D
TIOA3/4
TIOB3/4
TIOC3/4
TIOD3/4
Module data bus
Legend:
TSTR: Timer start register (16 bits)
TMDR: Timer mode register (8 bits)
TCR: Timer control register (8 bits)
TIOR: Timer I/O control register (8 bits)
TSRD: Timer status register D (8 bits)
TIERD: Timer interrupt enable register D (8 bits)
TCNT: Free-running counter (16 bits)
GR: General register (16 bits)
Interrupts:
OVI: Overflow interrupt
IMI: Input capture/compare-match interrupt
Note: * TMDR is used by channels 3 to 5.
TSRDH and TIERDH are used by channel 3.
TSRDL and TIERDL are used by channels 4 and 5.
Figure 10.5 Block Diagram of Channels 3 and 4
Rev. 5.00 Jan 06, 2006 page 204 of 818
REJ09B0273-0500