SH7050 Datasheet, PDF (265/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
Bit 0—Input Capture/Compare-Match Flag (IMF3A): Status flag that indicates GR3A input
capture or compare-match.
Bit 0:
IMF3A
0
1
Description
[Clearing condition]
(Initial value)
When IMF3A is read while set to 1, then 0 is written in IMF3A
[Setting conditions]
• When the TCNT3 value is transferred to GR3A by an input capture signal while
GR3A is functioning as an input capture register
• When TCNT3 = GR3A while GR3A is functioning as an output compare register
TSRDL indicates the status of channel 4 and 5 input capture, compare-match, and overflow.
Bit: 7
6
5
4
OVF4 IMF4D IMF4C IMF4B
Initial value: 0
0
0
0
R/W: R/(W)* R/(W)* R/(W)* R/(W)*
Note: * Only 0 can be written, to clear the flag.
3
IMF4A
0
R/(W)*
2
OVF5
0
R/(W)*
1
IMF5B
0
R/(W)*
0
IMF5A
0
R/(W)*
Bit 7—Overflow Flag (OVF4): Status flag that indicates TCNT4 overflow.
Bit 7:
OVF4
0
1
Description
[Clearing condition]
When OVF4 is read while set to 1, then 0 is written in OVF4
[Setting condition]
When the TCNT4 value overflows (from H'FFFF to H'0000)
(Initial value)
Rev. 5.00 Jan 06, 2006 page 245 of 818
REJ09B0273-0500