SH7050 Datasheet, PDF (481/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 15 Compare Match Timer (CMT)
15.1.3 Register Configuration
Table 15.1 summarizes the CMT register configuration.
Table 15.1 Register Configuration
Channel Name
Abbreviation R/W
Initial
Value
Address
Access
Size (Bits)
Shared
0
Compare match
timer start register
Compare match
timer control/status
register 0
CMSTR
CMCSR0
R/W H'0000 H'FFFF83D0 8, 16, 32
R/(W)^* H'0000 H'FFFF83D2 8, 16, 32
Compare match
timer counter 0
CMCNT0
R/W
H'0000 H'FFFF83D4 8, 16, 32
Compare match
timer constant
register 0
CMCOR0
R/W H'FFFF H'FFFF83D6 8, 16, 32
1
Compare match
CMCSR1
R/(W)^* H'0000 H'FFFF83D8 8, 16, 32
timer control/status
register 1
Compare match
timer counter 1
CMCNT1
R/W
H'0000 H'FFFF83DA 8, 16, 32
Compare match
timer constant
register 1
CMCOR1
R/W H'FFFF H'FFFF83DC 8, 16, 32
Notes: With regard to access size, two cycles are required for byte access and word access, and
four cycles for longword access.
* The only value that can be written to the CMCSR0 and CMCSR1 CMF bits is a 0 to
clear the flags.
Rev. 5.00 Jan 06, 2006 page 461 of 818
REJ09B0273-0500