SH7050 Datasheet, PDF (724/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Appendix A On-Chip Supporting Module Registers
Timer Status Register DL
(TSRDL)
H'FFFF8205
8
ATU
(Channels 3 to 5)
Bit: 7
6
5
4
Bit name: OVF4 IMF4D IMF4C IMF4B
Initial value: 0
0
0
0
R/W: R/(W)* R/(W)* R/(W)* R/(W)*
Note: * Only 0 can be written to clear the flag.
3
IMF4A
0
R/(W)*
2
OVF5
0
R/(W)*
1
IMF5B
0
R/(W)*
0
IMF5A
0
R/(W)*
Bit
Bit Name
Value Description
7
Overflow flag 0
[Clearing condition]
(Initial value)
(OVF4)
Read OVF4 when OVF4 =1, then write 0 in OVF4
1
[Setting condition]
TCNT4 overflowed from H'FFFF to H'0000
6
Input capture/ 0
[Clearing condition]
(Initial value)
compare match
Read IMF4D when IMF4D =1, then write 0 in IMF4D
flag (IMF4D)
1
[Setting conditions]
1. TCNT4 value is transferred to GR4D by an input capture
signal when GR4D functions as an input capture register
2. TCNT4 = GR4D when GR4D functions as an output
compare register
5
Input capture/ 0
[Clearing condition]
(Initial value)
compare match
flag (IMF4C)
1
Read IMF4C when IMF4C =1, then write 0 in IMF4C
[Setting conditions]
1. TCNT4 value is transferred to GR4C by an input capture
signal when GR4C functions as an input capture register
2. TCNT4 = GR4C when GR4C functions as an output
compare register
4
Input capture/ 0
[Clearing condition]
(Initial value)
compare match
flag (IMF4B)
1
Read IMF4B when IMF4B =1, then write 0 in IMF4B
[Setting conditions]
1. TCNT4 value is transferred to GR4B by an input capture
signal when GR4B functions as an input capture register
2. TCNT4 = GR4B when GR4B functions as an output
compare register
Rev. 5.00 Jan 06, 2006 page 704 of 818
REJ09B0273-0500