SH7050 Datasheet, PDF (264/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
Bit 3—Input Capture/Compare-Match Flag (IMF3D): Status flag that indicates GR3D input
capture or compare-match.
Bit 3:
IMF3D
0
1
Description
[Clearing condition]
(Initial value)
When IMF3D is read while set to 1, then 0 is written in IMF3D
[Setting conditions]
• When the TCNT3 value is transferred to GR3D by an input capture signal while
GR3D is functioning as an input capture register
• When TCNT3 = GR3D while GR3D is functioning as an output compare register
Bit 2—Input Capture/Compare-Match Flag (IMF3C): Status flag that indicates GR3C input
capture or compare-match.
Bit 2:
IMF3C
0
1
Description
[Clearing condition]
(Initial value)
When IMF3C is read while set to 1, then 0 is written in IMF3C
[Setting conditions]
• When the TCNT3 value is transferred to GR3C by an input capture signal while
GR3C is functioning as an input capture register
• When TCNT3 = GR3C while GR3C is functioning as an output compare register
Bit 1—Input Capture/Compare-Match Flag (IMF3B): Status flag that indicates GR3B input
capture or compare-match.
Bit 1:
IMF3B
0
1
Description
[Clearing condition])
(Initial value)
When IMF3B is read while set to 1, then 0 is written in IMF3B
[Setting conditions]
• When the TCNT3 value is transferred to GR3B by an input capture signal while
GR3B is functioning as an input capture register
• When TCNT3 = GR3B while GR3B is functioning as an output compare register
Rev. 5.00 Jan 06, 2006 page 244 of 818
REJ09B0273-0500