SH7050 Datasheet, PDF (319/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
CK
Internal write signal
1 written
to DST
DCNT start delay
Down-count start
flag DST
DCNT input clock
DCNT H'0005 H'0004 H'0003 H'0002 H'0001 H'0000 H'0000
One-shot pulse
output
1 state
1 state
Figure 10.23 One-Shot Pulse Function Pulse Output Timing
10.3.12 Offset One-Shot Pulse Function Pulse Output Timing
There is a delay of one CK state between the occurrence of a compare-match between the channel
1 or 2 free-running counter (TCNT) and a general register (GR), and setting of the channel 10
down-count start flag (DST) is set. In addition, there is a maximum delay of one DCNT input
clock count clock cycle between setting of the DST flag and the start of the DCNT count. One-
shot pulse output varies by a further delay of one CK state, but there is no error in the one-shot
pulse output pulse width.
Figure 10.24 shows an example with an offset width setting of H'0100, and a pulse width setting
of H'0003.
Rev. 5.00 Jan 06, 2006 page 299 of 818
REJ09B0273-0500