SH7050 Datasheet, PDF (96/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 6 Interrupt Controller (INTC)
6.1.2 Block Diagram
Figure 6.1 is a block diagram of the INTC.
IRQOUT
NMI
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
Input
control
UBC
DMAC
ATU
CMT
SCI
A/D
WDT
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
CPU/
DMAC
request
judg-
ment
Priority
ranking
judg-
ment
Com-
parator
Interrupt
request
SR
I3 I2 I1 I0
CPU
ICR
IPR
ISR
IPRA–IPRH
DTER
DTC
Module bus
Bus
interface
INTC
UBC: User break controller
DMAC: Direct memory access controller
CMT: Compare match timer
SCI: Serial communication interface
A/D: A/D converter
WDT: Watchdog timer
ICR: Interrupt control register
ISR: IRQ ststus register
DTER: DTC enable register
IPRA–IPRH: Interrupt priority level setting
registers A to H
SR: Status register
Figure 6.1 INTC Block Diagram
Rev. 5.00 Jan 06, 2006 page 76 of 818
REJ09B0273-0500