SH7050 Datasheet, PDF (127/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

7.5 Cautions on Use
Section 7 User Break Controller (UBC)
7.5.1 On-Chip Memory Instruction Fetch
Two instructions are simultaneously fetched from on-chip memory. If a break condition is set on
the second of these two instructions but the contents of the UBC break condition registers are
changed so as to alter the break condition immediately after the first of the two instructions is
fetched, a user break interrupt will still occur when the second instruction is fetched.
7.5.2 Instruction Fetch at Branches
When a conditional branch instruction or TRAPA instruction causes a branch, instructions are
fetched and executed as follows:
1. Conditional branch instruction, branch taken: BT, BF
TRAPA instruction, branch taken: TRAPA
Instruction fetch cycles: Conditional branch fetch → Next-instruction overrun fetch
→ Next-instruction overrun fetch → Branch destination fetch
Instruction execution: Conditional branch instruction execution → Branch destination
instruction execution
2. When branching with a delayed conditional instruction: BT/S and BF/S instructions
Instruction fetch order: Corresponding instruction fetch → next instruction fetch (delay
slot) → overrun fetch of instruction after next → branch destination instruction fetch
Instruction execution order: Corresponding instruction execution → delay slot instruction
execution → branch destination instruction execution
When a conditional branch instruction or TRAPA instruction causes a branch, the branch
destination will be fetched after the next instruction or the one after that does an overrun fetch.
However, because the instruction that is the object of the break first breaks after a definite
instruction fetch and execution, the kind of overrun fetch instructions noted above do not
become objects of a break. If data access breaks are also included with instruction fetch breaks
as break conditions, a break occurs because the instruction overrun fetch is also regarded as
becoming a data break.
Rev. 5.00 Jan 06, 2006 page 107 of 818
REJ09B0273-0500