SH7050 Datasheet, PDF (352/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
Contention between TCNT Write and Counter Clearing by Overflow: With channel 3 to 5
free-running counters (TCNT3 to TCNT5), if overflow occurs in the T2 state of a CPU write cycle
when clearing is enabled, the write to TCNT has priority and the counter is not cleared to H'0000.
Writing of 1 to the interrupt status flag (OVF) due to the overflow is performed in the same way as
for normal overflow.
The timing in this case is shown in figure 10.56. In this example, H'5555 is written at the point at
which TCNT overflows.
T1
T2
CK
TCNT input clock
Address
TCNT address
Internal write signal
Overflow signal
TCNT
FFFF
5555
(CPU write value)
5556
Interrupt status flag
(OVF)
Figure 10.56 Contention between TCNT Write and Overflow
Rev. 5.00 Jan 06, 2006 page 332 of 818
REJ09B0273-0500