SH7050 Datasheet, PDF (183/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 9 Direct Memory Access Controller (DMAC)
Indirect Address Transfer Mode: In this mode the memory address storing the data you actually
want to transfer is specified in DMAC internal transfer source address register (SAR3). Therefore,
in indirect address transfer mode, the DMAC internal transfer source address register value is read
first. This value is stored once in the DMAC. Next, the read value is output as the address, and the
value stored at that address is again stored in the DMAC. Finally, the subsequent read value is
written to the address specified by the transfer destination address register, ending one cycle of
DMAC transfer.
In indirect address mode (figure 9.9), transfer destination, transfer source, and indirect address
storage destination are all 16-bit external memory locations, and transfer in this example is
conducted in 16-bit or 8-bit units. Timing for this transfer example is shown in figure 9.10.
In indirect address mode, one NOP cycle (figure 9.10) is required until the data read as the indirect
address is output to the address bus. When transfer data is 32-bit, the third and fourth bus cycles
each need to be doubled, giving a required total of six bus cycles and one NOP cycle for the whole
operation.
Rev. 5.00 Jan 06, 2006 page 163 of 818
REJ09B0273-0500