SH7050 Datasheet, PDF (349/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
10.7 Usage Notes
Note that the kinds of operation and contention described below occur during ATU operation.
Contention between TCNT Write and Clearing by Compare-Match: With channel 3 to 9 free-
running counters (TCNT3 to TCNT9), if a compare-match occurs in the T2 state of a CPU write
cycle when clearing is enabled, the write to TCNT has priority and clearing is not performed.
The compare-match remains valid, and writing of 1 to the interrupt status flag and waveform
output to an external destination are performed in the same way as for a normal compare-match.
The timing in this case is shown in figure 10.53.
CK
Address
T1
T2
TCNT address
Internal write signal
Compare-match signal
Counter clear signal
TCNT
CPU write value
Interrupt status flag
External output signal
(1 output)
Figure 10.53 Contention between TCNT Write and Clear
Rev. 5.00 Jan 06, 2006 page 329 of 818
REJ09B0273-0500