SH7050 Datasheet, PDF (384/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 12 Watchdog Timer (WDT)
12.3.2 Interval Timer Mode
To use the WDT as an interval timer, clear WT/IT to 0 and set TME to 1. An interval timer
interrupt (ITI) is generated each time the timer counter overflows. This function can be used to
generate interval timer interrupts at regular intervals (figure 12.5).
TCNT value
H'FF
Overflow
Overflow
Overflow
Overflow
H'00
WT/IT = 0
ITI
ITI
ITI
ITI
TME = 1
ITI: Interval timer interrupt request generation
Figure 12.5 Operation in the Interval Timer Mode
Time
12.3.3 Clearing the Standby Mode
The watchdog timer has a special function to clear the standby mode with an NMI interrupt. When
using the standby mode, set the WDT as described below.
Before Transition to the Standby Mode: The TME bit in the TCSR must be cleared to 0 to stop
the watchdog timer counter before it enters the standby mode. The chip cannot enter the standby
mode while the TME bit is set to 1. Set bits CKS2 to CKS0 so that the counter overflow interval is
equal to or longer than the oscillation settling time. See section 22.3, AC Characteristics, for the
oscillation settling time.
Recovery from the Standby Mode: When an NMI request signal is received in standby mode,
the clock oscillator starts running and the watchdog timer starts incrementing at the rate selected
by bits CKS2 to CKS0 before the standby mode was entered. When the TCNT overflows (changes
from H'FF to H'00), the clock is presumed to be stable and usable; clock signals are supplied to the
entire chip and the standby mode ends.
For details on the standby mode, see section 21, Power-Down States.
Rev. 5.00 Jan 06, 2006 page 364 of 818
REJ09B0273-0500