SH7050 Datasheet, PDF (323/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
10.3.15 PWM Output Operation at Start of Channel 3 to 5 Counter
In channel 3 to 5 PWM mode, free-running counter (TCNT3 to TCNT5) PWM output is not 1 in
the first cycle when the counter is started. However, the interrupt status flag is set to 1 when there
is a match with the duty register value in the first cycle.
The timing in this case is shown in figure 10.27. In this example, H'0003 is set as the duty register
value, and H'0005 as the cycle register value.
Cycle
TCNT
0000 0001 0002 0003 0004 0005 0000 0001 0002 0003 0004 0005 0000 0001 0002 0003
TCNT input clock
Counter start signal
PWM output
Duty
Interrupt status flag
1st cycle
2nd cycle
Figure 10.27 Channel 3 to 5 PWM Output Waveform
3rd cycle
Rev. 5.00 Jan 06, 2006 page 303 of 818
REJ09B0273-0500