SH7050 Datasheet, PDF (146/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 8 Bus State Controller (BSC)
When the wait is specified by software using WCR, the wait input WAIT signal from outside is
sampled. Figure 8.5 shows the WAIT signal sampling. The WAIT signal is sampled at the clock
rise one cycle before the clock rise when T_w state shifts to T₂ state. When using external waits, use
a WCR setting of 1 state or more when extending CS assertion, and 2 states or more otherwise.
T₁
T_W
T_W
T_W0
T₂
CK
Address
CSn
Read
RD
Data
Write
WRx
Data
WAIT
Figure 8.5 Wait State Timing of Ordinary Space Access (Wait States from Software Wait 2
State + WAIT Signal)
Rev. 5.00 Jan 06, 2006 page 126 of 818
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