SH7050 Datasheet, PDF (296/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
10.2.13 Input Capture Registers (ICR)
The input capture registers (ICR) are 32-bit registers. The ATU has four 32-bit ICR registers in
channel 0.
Channel
0
Abbreviation
ICR0AH, ICR0AL,
ICR0BH, ICR0BL,
ICR0CH, ICR0CL,
ICR0DH, ICR0DL
Function
Dedicated input capture registers
Input capture registers 0AH, 0AL to 0DH, 0DL (ICR0AH, ICR0AL to ICR0DH, ICR0DL)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R R R R R R R R R R R R R R R R
The ICR registers are 32-bit read-only registers used exclusively for input capture.
These dedicated input capture registers store the TCNT0 value on detection of an input capture
signal from an external source. The corresponding TSR bit is set to 1 at this time. The input
capture signal edge to be detected is specified by timer I/O control register TIOR0A.
ICR0A and ICR0D can detect an external input capture (TIA0) or the channel 1 general register
(GR1A) compare-match signal (TRG1A) as an input capture signal.
The ICR registers are connected to the CPU via an internal 16-bit bus, and can only be accessed
by a longword read. Word reads cannot be used.
The ICR registers are initialized to H'00000000 by a power-on reset, and in hardware standby
mode and software standby mode.
Rev. 5.00 Jan 06, 2006 page 276 of 818
REJ09B0273-0500