SH7050 Datasheet, PDF (177/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 9 Direct Memory Access Controller (DMAC)
Figure 9.4 shows the example of changes in priority levels when transfer requests are issued
simultaneously for channels 0 and 3, and channel 1 receives a transfer request during a transfer on
channel 0. The DMAC operates in the following manner under these circumstances:
1. Transfer requests are issued simultaneously for channels 0 and 3.
2. Since channel 0 has a higher priority level than channel 3, the channel 0 transfer is conducted
first (channel 3 is on transfer standby).
3. A transfer request is issued for channel 1 during a transfer on channel 0 (channels 1 and 3 are
on transfer standby).
4. At the end of the channel 0 transfer, channel 0 shifts to the lowest priority level.
5. At this point, channel 1 has a higher priority level than channel 3, so the channel 1 transfer
comes first (channel 3 is on transfer standby).
6. When the channel 1 transfer ends, channel 1 shifts to the lowest priority level.
7. Channel 3 transfer begins.
8. When the channel 3 transfer ends, channel 3 and channel 2 priority levels are lowered, giving
channel 3 the lowest priority.
Transfer request Channel waiting DMAC operation
Issued for
channels 0 and 3
Issued for channel 1
3
Channel 0
transfer begins
Change of
1.3
Channel 0
priority
transfer ends
Channel 1
transfer begins
Change of
3
Channel 1
priority
transfer ends
Channel priority
0>1>2>3
1>2>3>0
2>3>0>1
None
Channel 3
transfer begins
Channel 3
transfer ends
Change of
priority
0>1>2>3
Figure 9.4 Example of Changes in Priority in Round Robin Mode
Rev. 5.00 Jan 06, 2006 page 157 of 818
REJ09B0273-0500