SH7050 Datasheet, PDF (257/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
Bit 1—Interval Interrupt Flag (IIF1): Status flag that indicates the generation of an interval
interrupt.
Bit 1:
IIF1
0
1
Description
[Clearing condition]
When IIF1 is read while set to 1, then 0 is written in IIF1
[Setting condition]
When 1 is generated by AND of ITVE1 in ITVRR and bit 11 of TCNT0L
(Initial value)
Bit 0—Interval Interrupt Flag (IIF0): Status flag that indicates the generation of an interval
interrupt.
Bit 0:
IIF0
0
1
Description
[Clearing condition]
When IIF0 is read while set to 1, then 0 is written in IIF0
[Setting condition]
When 1 is generated by AND of ITVE0 in ITVRR and bit 10 of TCNT0L
(Initial value)
TSRAL indicates the status of channel 0 input capture and overflow.
Bit: 7
6
5
4
—
—
—
OVF0
Initial value: 0
0
0
0
R/W: R
R
R R/(W)*
Note: * Only 0 can be written, to clear the flag.
3
ICF0D
0
R/(W)*
2
ICF0C
0
R/(W)*
1
ICF0B
0
R/(W)*
0
ICF0A
0
R/(W)*
Bits 7 to 5—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 4—Overflow Flag (OVF0): Status flag that indicates TCNT0 overflow.
Rev. 5.00 Jan 06, 2006 page 237 of 818
REJ09B0273-0500